Designing an integrated circuit using a hardware description language and a logic synthesis tool has a number of advantages:

• Significantly reduced design time
• Vendor and technology independence
• Simplified design modification
• Fast source code simulation

Our models use only the synthesizable subset of Verilog HDL, and can be used with any logic synthesis tool that supports Verilog. We usually use the logic synthesis tools from Synopsys (for full custom), Synplicity (for FPGAs) and Exemplar (for ASICs).