Systemyde (pronounced system-wide) International Corporation develops Intellectual Property (IP), in the form of synthesizable Verilog HDL models.

My Verilog HDL designs are suitable for FPGA, ASIC or full custom implementations.

I designed all five generations of Rabbit microprocessors and my contract with Rabbit Semiconductor gives Systemyde full core rights to these designs.

The first three generations are completely foundry- and technology-independent, while portions of last two generations are currently tied to a specific technology/fab because of analog IP.

With the Rabbit designs, I wrote the specification, did the majority of the architectural work, wrote all (or almost all, for the 5000 and 6000) of the Verilog HDL, wrote the testbenches and simulation/test vectors, defined and inserted test controllers, prepared the designs for scan insertion, and contributed to timing closure.