Current NEWT technical manual.

The replacement CPU board ready to be debugged.

The replacement CPU board reverse side.

Time to get out the oscilloscope....

08/17/2010 Status:
Deep Sleep: 310uA, Light Sleep: 4.2mA, Run: 7.9mA
Register read timing change verified.
"Loop of addition" benchmark:
1x: 1055
2x: 1913
5x: 4153
10x: 6538
20x: 9179
50x: 12022

08/14/2010 Status:
Light Sleep current drain reduced by disabling clock.
Register read timing changed to improve Turbo mode
performance. Need to verify.
First production components ordered.

08/06/2010 Status:
Investigating if it's possible to change the design to do
register writes at turbo speed, which will improve turbo
performance.
Also investigating ways to improve Light Sleep current drain.

08/02/2010 Status:
Found the light sleep current drain - floating data bus.
Deep Sleep: 330uA; Light Sleep: 6mA; Run: 7.7mA (no turbo)
Almost ready to order first production batch!

07/29/2010 Status:
Light Sleep current isn't from FPGA after all. Still looking.
Software for PEEK and POKE for I/O do bytes. Need to modify to
do words.

07/23/2010 Status:
PLUGx only works correctly with 4K modules. Software issue.
Had to delete 4-byte transmit buffer to make room for changes.

07/22/2010 Status:
User mode operation fixed. Problem was with c=regn instruction.
PLUG3 issue is a software bug.
Updated spec posted to site.

07/20/2010 Status:
User mode doesn't work. Machine hung when I tried to PLUG the
Real Estate module into Port 3.

07/19/2010 Status:
Turbo mode works!!

07/16/2010 Status:
The MMU seems to work.
Module images can be plugged into ports and unplugged from ports!
Turbo mode does not work.
Still no resolution to the power issue, but problem when eliminating
continuous reset may be due to dpwo signalling with display drivers.

07/13/2010 Status:
POKE works... just not with an on-chip peripheral address. Grr...
Eliminating continuous Reset during Light Sleep works in sim but not
in the FPGA. More grr...

07/10/2010 Status:
90% sure that Light Sleep power issue must be due to FPGA being
held in Reset during this time. Hmm...
Added option to enable/disable MMU via peripheral write. Necessary
because of error in the code in Flash. Will test next.
Verified that POKE works. Looks like block copy works.
Fixed Bank Select and Turbo state so they're preserved in Light Sleep.

07/09/2010 Status:
Still haven't found the light sleep power issue.
Corrected an issue with updating register address and PFAD
Corrected the WCMD instruction write cases, so now POKE works.
Corrected the WCMD instruction read cases, so now PEEK works.
The bank switch bits are not preserved during light sleep. Investigating.
Still haven't changed the clock to stop during light sleep.
Getting POKE to work means that I can now test the Turbo modes and
program the MMU to verify the PLUG and UNPLUG commands!

07/07/2010 Status:
Model of display chip working. Makes simulation easier. Also means
that I can build an interface to a different display. LEDs?

07/04/2010 Status:
Oops, the MMU was being disabled by light sleep. That's fixed.
Also the data bus and the isa bus were both being driven during
light sleep. Is that the source of the current drain during light
sleep? We'll see. Need to disable the clock inside the FPGA during
light sleep. That will save 5-10mA.

07/03/2010 Status:
The flag output wasn't initialized during light sleep or deep sleep.
Since the Actel flip-flops like to power-up holding a one, that
meant the output was always High until a TONE or BEEP. Not sure
how that would affect the piezo buzzer. Fixed.

07/02/2010 Status:
The problem with running programs has been found. The CLRST
was clearing all 12 bits of the ST register.