The FPGA can be reprogrammed using the Actel FlashPro software
and hardware.

FPGA programming file (.pdb) 07/15/2011 version

The Flash memory on the board can be programmed via JTAG. This
requires a BSDL file to describe the JTAG chain configuration and
a configuration file that describes the connection between the FPGA
and the Flash memory.

BSDL file for the Actel device (.bsd)

Flash configuration file for the 41CL board (.topflash)

Downloading to the 41CL needs a program to transfer data from the
PC. Raymond Wiker wrote this .NET program for just this purpose.
Compile the program (using your path and version):

C:\WINDOWS\Microsoft.NET\Framework\v4.0.30319\csc.exe /t:exe CLWriter.cs

CLWriter source (.cs)

Antti Louko wrote these Python scripts for uploading and downloading
when using Linux. The data is read and written in hex for easy post-
processing, which means you can't use a .rom file directly.

./write1.py /dev/ttyUSB0 4800 < Hex-file.hex
./read1.py -f Output-file.hex /dev/ttyUSB0 9600

Script for download to 41CL (.py)

Script for upload from 41CL (.py)