We provide only robust synthesizable models. The complete design package includes:

• The synthesizable model
• A Verilog HDL testbench for verification of the model
• A test suite, suitable for both silicon verification and test.
• The necessary synthesis constraint files
• Complete user documentation

Technical information about our microprocessor and peripheral designs is provided on subsequent pages. All of our on-line documentation is supplied in Adobe Portable Document Format. A free copy of the required viewer is available from Adobe.