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| We use only PC-based tools: For Verilog simulation we use Fusion/VCSi from Viewlogic. For synthesis we use Synplify from Synplicity.
Currently Synplify only targets FPGAs, but is capable of verifying that a design targeted
for an ASIC can be synthesized, in addition to allowing prototyping. To prove the functionality of our cores, we implement them in FPGAs. We have used Xilinx , Altera and Actel for this prototyping, but we only have the Xilinx
tools in-house. |
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| 12/29/2002 | © Copyright 2002, Systemyde International Corporation | |||||||||||||