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We use only PC-based tools: For Verilog simulation we use Fusion/VCSi from Viewlogic. For synthesis we use Synplify from Synplicity. To prove the functionality of our cores, we implement them in FPGAs. We have used
Xilinx , Altera and
Actel for this prototyping,
but we only have the Actel and Xilinx tools in-house. |
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| 05/26/2009 | © Copyright 2009, Systemyde International Corporation | |||||||||||||